CD4073 Triple 3-Input AND Gate IC DIP-14 Package

CD4073 AND gates, provide the system designer with direct implementation of the AND function and supplement the existing family of CMOS gates.

The CD4073 types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

Features:-

• Medium-Speed Operation - t _PLH , t _PHL = 60 ns (typ.) at V _DD = 10 V
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 µA at 18 V over full package-temperature range: 100 nA at 18 V and 25°C
• Noise margin (full package-temperature range) =
  • 1 V at V _DD = 5 V
  • 2 V at V _DD = 10 V
  • 2.5 V at V _DD = 15 V
• Standardized, symmetrical output characteristics
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

Specifications:-

Parameter	Specification
Part number	CD4073
Technology Family	CD4000
VCC (Min) (V)	3
VCC (Max) (V)	18
Channels (#)	3
Inputs per channel	3
IOL (Max) (mA)	6.8
IOH (Max) (mA)	-6.8
Input Type	Standard CMOS
Output Type	Push-Pull
Rating	See Data Sheet
Operating temperature range (C)	-55 to 125
Package Group	PDIP|14
Features	Standard Speed (tpd > 50ns)
Data rating (Max) (Mbps)	8
Package size: mm2:W x L (PKG)	14PDIP: 181 mm2: 9.4 x 19.3 (PDIP|14)

Related Document:-

CD4073 IC Datasheet